VERILOG仿真调度模型实例讲解
摘要
调度的;针对仿真模型再CPU上运行的特性,对RTL设计,有反向指导意义。
关键词
全文:
PDF参考
[1]C. Spear, SystemVerilog for Verification. 2nd ed. San
Jose, CA: Springer, 2015.
[2]A. B. Smith,“A formal semantics for Verilog-VHDL
simulation,”IEEE Transactions on Computers, vol. 45, no. 3,
pp. 345-356, Mar. 1996.
[3]C. E. Cummings,“Verilog Nonblocking Assignments
With Delays, Myths & Mysteries,”DesignCon 2000, Santa
Clara, CA, Jan. 2000.
[4]S. L. Tripathi, S. Saxena, S. K. Sinha, and G. S. Patel,
Digital VLSI Design and Simulation with Verilog. 1st ed.
New York, NY: McGraw-Hill, 2018.
[5]J. Doe,“Behavioral Modeling using Verilog-A,”
IEEE Workshop on Signal Processing Systems, pp. 123-134,
Oct. 2005.
[6]IEEE Std 1364-2001, IEEE Standard Verilog
Hardware Description Language, 2001.
[7]IEEE Std 1800-2017, IEEE Standard for
SystemVerilog- Unified Hardware Design, Specification and
Verification Language, 2017.
[8]J. Bergeron, E. Cerny, A. Hunter, and A. Nightingale,
Verification Methodology Manual for SystemVerilog. 3rd ed.
San Jose, CA: Springer, 2019.
[9]M. N. Buss, The Designer’s Guide to Verilog-AMS.
1st ed. Norwell, MA: Kluwer Academic Publishers, 2002.
[10]P. A. Sturman, The Designer’s Guide to SPICE
and Spectre. 2nd ed. Norwell, MA: Kluwer Academic
Publishers, 2004.
Refbacks
- 当前没有refback。
